The hardest part of chip architecture was never mastering some arcane secret — it’s deciding what to do and what not to do under real constraints. The question is how to design a computer that can actually be used at scale, not a machine that only works with the most advanced process node, the deepest pockets, and the most specialized team.
Parents in town for hooding and travel—notes from my first real break after work on why shipping silicon is largely a management problem, slow feedback loops in hardware, the mindset behind heavy AI use, and why we need a better AI computer, not a faster niche accelerator.
Three questions on the ARM vs. RISC-V battle — what RISC-V actually has going for it in the AI era, why ARM is now making its own SoC, and where RISC-V still has ground to cover.
AI-native workloads, edge fragmentation, and faster experimentation are pushing architecture back to the center of hardware value creation.
As prototyping, validation, and silicon feedback loops shrink from months to days, chip development will start to move at a cadence much closer to software.