Problem

In heterogeneous systems, the bus between a host and its accelerators sets the pace. Past work raised bus bandwidth for data-hungry workloads. Many accelerators are latency-sensitive instead: each request waits a full round trip before the next one starts.

Idea

Zipper is a protocol optimization layer on top of existing bus standards. It lets a device issue requests in parallel at the device and request level, and it exploits data locality. The bus round trip then overlaps with useful work.

baselinereq 1waitresp 1req 2waitresp 2Zipperreq 1req 2req 3resp 1resp 2resp 3overlapped requests hide bus latency
Baseline transactions wait for each response. Zipper overlaps them.

Result

We built the end-to-end system on a heterogeneous platform with an integrated FPGA and applied Zipper to two domains.

8×speedup for one accelerator
4.3%logic overhead for that speedup
1.5×speedup for a second accelerator, at 0.9% overhead

My role

First author. I designed the protocol layer, built the FPGA system, and ran the evaluation.

Paper: ASP-DAC 2025