Zipper: hiding bus latency for accelerators
A protocol layer that overlaps bus requests and exploits locality, so latency-sensitive accelerators keep running instead of waiting on the bus.
Research
Case studies from my PhD and research work: the problem, the idea, and the result.
Twine: one interface for heterogeneous hardware
A Chisel extension that standardizes component interfaces and generates the control logic, so designers compose systems instead of wiring them.
Overpass: interconnect bandwidth for diverse components
A flexible interconnect with distributed resource allocation, so CPUs, accelerators, and I/O share bandwidth without one central arbiter.
Formally verifying a low-trust architecture
A complete formal verification of the Sequestered Encryption architecture, from the ISA down to RTL. CCS 2023 Distinguished Paper Award.
Morpheus: a moving target for attackers
A RISC-V secure architecture that keeps re-randomizing code and pointers underneath the running program, so attack probes go stale before they can be used.