With the stagnation of Moore’s Law and the breakdown of Dennard Scaling, hardware designers are increasingly turning to heterogeneous architectures to achieve higher performance and energy efficiency. Heterogeneous systems, however, incur greater non-recurring engineering (NRE) effort, higher communication overhead, and increased memory bandwidth contention. A primary contributor is inefficient communication among heterogeneous components: mismatched I/O interfaces hinder reusability and drive up NRE, poor latency tolerance creates performance bottlenecks, and inadequate resource allocation leads to contention and interference.
This dissertation presents minimally invasive solutions to these communication challenges. Twine is a design language that standardizes communication interfaces and automates control logic generation; it reduces design specification size by 3×. Zipper is a set of latency-tolerant bus optimizations that let systems tolerate microsecond-level delays without drastic redesign; it delivers up to 8× performance gains. Overpass is a flexible interconnect system with distributed resource allocation; it increases system performance by 35%. Together, they form a cohesive framework for the core communication bottlenecks of heterogeneous hardware at different design stages.
Doctoral committee: Prof. Todd Austin (Chair), Prof. Valeria Bertacco, Prof. Jean-Baptiste Jeannin, and Prof. Georgios Tzimpragos (University of Wisconsin–Madison).